1. Field of the Invention
The present invention relates to a semiconductor device and the fabricating method thereof. More particularly, it relates to a semiconductor structure with partially etched gate and method of fabricating the same.
2. Description of the Related Art
In general, the gate structure of a metal oxide semiconductor field effect transistor (MOSFET) device is composed of a metal layer and an oxide layer stacked on a semiconductor substrate. Typically, the metal layer is substituted with a polysilicon layer to act as a gate conductive layer of the gate structure because of poor adhesion between metal and the oxide layer. However, the resistance of polysilicon materials is higher than that of the metal such that the polysilicon layer is usually doped with impurities to lower the resistance thereof. After doping with impurities, the conductivity of the polysilicon layer is reduced but not low enough to act as a conductive layer. A possible solution is to form a metal silicide layer such as tungsten silicide (WSi) layer thereon for improving gate conductivity. In addition, a cap layer is further disposed over the metal silicide layer of the gate structure, and a lining layer and spacers are respectively disposed beside the gate structure to insulate conductive materials thereof. Preferably, the cap layer and the spacer material can be silicon nitride to provide better insulation.
After formation of the gate structure of individual MOSFET device, which acts as a wordline (WL), a thick insulating layer (typically borophosphatesilicate glass (BPSG)) is formed over the wordline. Then an opening is etched through the insulating layer to the substrate between two adjacent wordlines by conventional photolithography and etching. Conductive material is then filled in the opening to form a contact node that connects the follow-up devices such as a bitline. The described process is the so-called “self-aligned contact” (SAC) opening process and is a frequently used semiconductor fabrication procedure.
Nevertheless, during formation of the SAC opening, the spacers are exposed and inevitably removed in part and conductive materials of the gate structure are still protected by the spacers and are not revealed. Once the conductive materials of the gate structure are revealed, an undesirable connection between the gate structure and the bitline contact (CB) can thus occur, referring to a so-called “CB to WL short”, and the MOSFET device and the electrical performance thereof cannot be achieved. Conventional semiconductor fabrication often results in over-etched spacers thus revealing the conductive materials of the gate structure causing the so-called “CB to WL short” which results in product loss. In other aspect, another so-called “CB open” can also occur between an insufficiently etched opening of the contact, causing disconnections between the MOSFET device and devices formed in follow-up processes.
Moreover, the aspect ratio between two adjacent gate structures is enlarged, with a shorter distance therebetween due to the increased device integration. Thus, voids in a poorly formed inter-layer dielectric (ILD) layer can cause undesirable shorts between two adjacent contacts such as the bitline contacts during the filling of conductive materials in a subsequent process, so called “CB to CB short”, causing device loss and decreased yield.
Thus, a better semiconductor structure for preventing the described undesirable shorts or openings is called for.